This invention relates to a method of manufacturing a semiconductor substrate, and more particularly to a method of manufacturing a semiconductor substrate applied to a semiconductor device having, e.g., a dielectric isolation structure.
Hitherto, in forming circuit elements of a semiconductor integrated circuit, in order to form circuit elements isolated from other circuit elements to form an island, a dielectric isolation system of a structure in which, e.g., each periphery (side surface and bottom surface) of the circuit elements is perfectly enclosed by a dielectric substance has been proposed. In accordance with the P-N junction isolation system having such a structure, the element isolation withstand voltage has been able to take more than 500 volts, whereas that withstand voltage could not take more than 200 volts according to the technologies prior thereto. Thus, this isolation system is advantageous, in that it is free from the problem of latch-up phenomenon taking place by the parasitic element operation, and that high integration is easy. For this reason, such a dielectric isolation system has been frequently used.
FIG. 4 is a cross section of an a semiconductor device having such a dielectric isolation structure. A semiconductor active layer is formed in a semiconductor layer 2 on the upper layer side of a first semiconductor substrate 1, and an insulating film (dielectric film) 3, e.g., silicon dioxide (SiO.sub.2) is formed on the lower layer side thereof. Furthermore, a second semiconductor substrate 4 is bonded to the first semiconductor substrate 1 in a manner that it serves as a underlying layer of the insulating film 3. More particularly, within the semiconductor layer 2 and an overlying layer, i.e., a layer formed thereabove, the essential parts of circuit elements 5 and 6 are formed. Within the semiconductor layer 2, a high concentration, i.e., heavily doped p-type silicon layer 7, a p-type silicon layer 8, and an n-type silicon layer 9 are formed in the a manner stacked in order recited.
It is to be noted that a high concentration n-type silicon layer 10 is formed as a buried layer at a portion between the p-type silicon layer 8 and the n-type silicon layer 9. Further, a p-type silicon layer 11, a high concentration n-type silicon layer 12 and a high concentration p-type silicon layer 13 are formed in a manner spaced from each other at the surface portion of the n-type silicon layer 9, and high concentration n-type silicon layer 14 and 15 are formed at the surface portions of the p-type silicon layer 11 and the high concentration p-type silicon layer 13 and within their regions, respectively.
Moreover, the circuit elements 5 and 6 are isolated at their bottom surfaces by the insulating film 3. Furthermore, the circuit elements 5 and 6, and adjacent other circuit elements are isolated at their side surfaces by providing grooves on all sides thereof. Namely, respective circuit elements are isolated by surrounding the peripheral portions thereof by means of a structure like a wall such that those circuit elements are surrounded by insulating films (dielectric films), respectively including polycrystalline silicon layers therein, 16 and 17, e.g., SiO.sub.2 along both the side surfaces of the grooves provided on all sides, and that polycrystalline silicon layers 18 are formed in the respective grooves.
It is point particularly important for a semiconductor substrate in forming a semiconductor device having such a dielectric isolation structure is that the surface flatness of the semiconductor layer 2, especially the n-type silicon layer 9 serving as the uppermost semiconductor layer where the essential parts of the circuit elements are directly formed is satisfactory, and that the film thickness is uniformly and precisely controlled. For example, when a predetermined thickness of this layer is assumed to be, e.g., 15 .mu.m, it is desirable that unevenness be within .+-.5%, i.e., .+-.0.75 .mu.m. In the case where the accuracy of this semiconductor layer thickness is poor, the characteristics of the circuit elements do not become uniform, and/or isolation between circuit elements cannot be completely carried out, so the element isolation withstand voltage cannot take a sufficiently large value. As a result, an adverse influence may be placed by adjacent elements conducting undesirably.
Meanwhile, in order to manufacture such a conventional semiconductor substrate, an approach is employed to form, within the semiconductor layer 2, high concentration p-type silicon layer 7, p-type silicon layer 8 and n-type silicon layer 9, as shown in FIG. 4, to form grooves thereafter to deposit polysilicon layers so that those grooves are sufficiently filled with such layers to regulate or adjust the thickness of the n-type silicon layer 9 of the uppermost layer by grinding. This grinding is carried out ordinarily at two stages, rough grinding and finish grinding.
In a conventional semiconductor substrate formed in accordance with such a manufacturing method, even if substrates having good flatness are used for the first semiconductor substrate 1 and the second semiconductor substrate 4, unevenness thickness becomes great because the n-type silicon layer 9 is formed by grinding.
The distribution of unevenness by the conventional method is shown at the right side portion of FIG. 3. In this figure, the internal unevenness is taken on the abscissa and the frequency is taken on the ordinate. In the case of a semiconductor substrate by the above-mentioned conventional method, when the thickness of the n-type silicon layer 9 is formed so that the diameter is 100 mm and a predetermined thickness of 15 .mu.m is measured, the internal unevenness takes a large value of 3 .mu.m (.+-.10) even if a good sample is taken, and the range of unevenness is also broad. At this time, the mean value of the internal distribution of the unevenness value is 4 .mu.m (.+-.13.3%). In accordance with such a conventional method, it is extremely difficult to provide a semiconductor substrate such that the internal unevenness falls within .+-.5% for realizing a perfect dielectric isolation structure.
In addition, in order to form an n-type silicon layer 9 of a predetermined thickness, it is required to additionally and thickly grow an epitaxial layer in excess of a predetermined thickness, e.g., 15 .mu.m by 40 .mu.m as a machining clearance for grinding or polishing at the succeeding process steps. As a result, it takes much time, resulting in lowered throughput. This causes costs to increase.